1. Field of the Invention
The present invention generally relates to a method for manufacturing a wafer-level semiconductor package, and more particularly to a method for manufacturing a semiconductor micro device package with a hermetical cavity.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP) and flip chips. Both of them greatly increase the packaging efficiency and significantly reduce the amount of board real estate required when compared to the alternative ball grid array (BGA) and thin small outline package (TSOP). However, as compared with conventional BGA or TSOP, CSP has the disadvantage of higher manufacturing cost. However, this problem could be eliminated if the chip-sized packages could be mass produced more easily. Therefore, the semiconductor packaging industry has tried to develop mass production techniques at the wafer-level for manufacturing the chip-sized packages, as illustrated in U.S. Pat. No. 5,323,051, U.S. Pat. No. 5,925,936 and U.S. Pat. No. 6,004,867. These wafer-level package techniques can not only increase the throughput but also reduce the contamination on the wafer surface since its package process can proceed before the wafer-dicing process. Therefore, a flip chip wafer-level package technique is applied to a semiconductor micro device package recently.
In conventional wafer-level package techniques, there are three main types of wafer-to-wafer bonding methods which include the silicon fusion method, the anodic bonding method, and the intermediate-layered bonding method. FIGS. 1a-1b are schematic views of the silicon fusion method for bonding two wafers formed of silicon, wherein FIG. 1a depicts that a lower wafer 11 and an upper wafer 21 are closely faced with their respective hydrophilic surfaces opposite to each other and the hydrophilic surfaces must be relatively even and clean with the roughness below 10A and the curvature smaller than 5 mm so as to ensure the surface quality of the wafer bonding, and FIG. 1b depicts that the opposite surfaces of the lower wafer 11 and the upper wafer 21 are brought together and pressed with a force concentrated in the center of the wafers such that the lower wafer 11 and the upper wafer 21 initiate a contact and bond to each other by the attraction (formed as hydrogen bonding) between the hydrophilic surfaces, and the center contact produces a bonding wave over the whole wafer surfaces so as to tighten the contact of the wafer surfaces. The wafers, then, are heated at a temperature in the range 300 to 800° C. so as to dehydrate the hydrophilic surfaces to form a bonding as strong as a silicon crystal structure. There are generally two drawbacks in the silicon fusion bonding method. Firstly, since the silicon fusion bonding is processed in a high temperature and the general wafers having integrated circuits, passive components (i.e., resistors, capacitors, and the like) or MEMs (micro-electro mechanical system) active components are not high temperature-resistant, the bonding method is not applicable for those wafers having semiconductor devices. Secondly, since this bonding method strictly requires a highly clean and flat bonding surface, it not only increases the manufacturing cost, but also not applicable for packaging wafers having semiconductor micro devices.
FIG. 2 is a schematic view of a conventional anodic bonding method which is generally applied in bonding a silicon wafer and a glass substrate. The anode is connected with the silicon wafer, the cathode is connected to the glass substrate and a voltage ranging from 50 V to 1200 V is applied such that the silicon wafer and the glass substrate become ionized and generate ion migration so as to build up an intense electric field for approaching and bonding, with the bonding temperature around 1000° C., the silicon wafer and the glass substrate. However, the anodic method has following drawbacks. Since the anodic method needs to proceed in a high bonding temperature, the anodic method is also not applicable for bonding a wafer having semiconductor micro devices and a glass substrate. Furthermore, it also has the thermal mismatch problem.
FIG. 3 is a schematic view of a conventional intermediate-layered bonding method. It can be seen that an upper wafer (or chip) 31 is bonded to a lower wafer 11 by an intermediated layer 15 to form a plurality of hermetical cavity 25. The intermediated layer 15, typically utilizing polyimide, epoxy, or anisotropic conductive adhesive film (ACF) as its material, is pre-disposed on the peripheral portion of each chip of the lower wafer 11 by printing or photolithography techniques, and then the upper wafer 31 and the lower wafer 11 are bonded together by thermo-compression. The advantage of the intermediate-layered bonding method is that the bonding process proceeds in low temperature below 150° C. The drawbacks of the intermediate-layered bonding method are as follows. First, since the intermediated layer 15 is generally consisted of an organic material, the hermetical cavity 25 is not fully sealed, and moisture can easily permeate into the hermetical cavity 25, which is not applicable for those packages having semiconductor micro devices and requiring hermetic reliability. Secondly, the material, such as epoxy, tends to have outgasing problem, which disadvantageously affects the hermetic and vacuum reliability of the hermetical cavity 25.
Therefore, it is needed to provide a method of manufacturing a wafer-level semiconductor micro device package so as to solve the above-mentioned problems in the prior art.